FIG. 10 is a plan view showing a semiconductor integrated circuit, a high frequency switch, as an example of a semiconductor integrated circuit utilizing a dielectric substrate in accordance with the prior art. In FIG. 10, reference character Q.sub.1 designates a field effect transistor (hereinafter referred to as `FET`) constructed on a dielectric substrate 1, which has a source S, a gate G, and a drain D. A first transmission line T.sub.1 is connected to the gate G of the FET Q.sub.1 and the electric length thereof is usually established at one fourth wavelength of the microwave signal, which enables impedance matching of the first transmission line T.sub.1 with the gate G. A capacitor C.sub.1 is connected to the first transmission line T1 and this is also connected to the grounding bonding pad P.sub.2. A gate bias bonding pad P.sub.1 is provided in contact with the node of the first transmission line T.sub.1 and the first capacitor C.sub.1. A second transmission line T.sub.2 is connected to the source S of the FET Q.sub.1. A via-hole V is provided for connecting the second transmission line T.sub.2 with a rear surface electrode 4 produced at the rear surface of the dielectric substrate 1. Reference characters M.sub.1 and M.sub.2 designate transmission lines connected to the source S and the drain D of the FET Q.sub.1, respectively.
FIG. 11 is a cross sectional view showing the device of FIG. 10 and schematically shows the FET, the via-hole, the connecting relation between them, and the transmission lines T.sub.1 and T.sub.2. FIG. 11 does not completely coincide with the plane pattern of FIG. 10. In FIG. 11, reference numeral 2 designates a semiconductor layer such as GaAs produced on a dielectric substrate 1 by an epitaxial growth method. An operating layer 3 of the FET Q.sub.1 is produced in the semiconductor layer 2 by implanting n conductivity type dopant impurities such as silicon by ion implantation. A source electrode S and a drain electrode D are produced on the operating layer 3 and a gate electrode G is produced on the operating layer 3 and deposed between the gate and drain electrodes. Here, an insulating substrate comprising such as sapphire or alumina is used for the dielectric substrate 1, gold-germanium alloy is used for the source S and the drain D electrodes which are in ohmic contact with the operating layer 3, and aluminum is used for the gate electrode G which forms a Schottky barrier contact with the operating layer 3. The transmission lines M.sub.1, M.sub.2, T.sub.1, and T.sub.2 comprise metal material. Reference numeral 5 designates an insulating film on which the transmission lines T.sub.1 and T.sub.2 are produced. The other same reference numerals as those shown in FIG. 10 designate the same parts.
FIG. 12 shows an equivalent circuit of the above-described semiconductor integrated circuit. An RF input terminal 7 and an RF output terminal 8 are connected to the transmission lines M.sub.1 and M.sub.2, respectively. A gate bias voltage power supply 9 is connected to the gate bias bonding pad P.sub.1. The other reference numerals that are the same as those shown in FIGS. 10 and 11 designate the same portions.
The operation will be described with reference to the equivalent circuit shown in FIG. 12.
A high frequency signal such as microwave signal is input to the RF input terminal 7, supplied to the FET Q.sub.1 through the transmission line M.sub.1, and output from the RF output terminal 8 through the transmission line M.sub.2.
The transmission line T.sub.1 and the capacitor C.sub.1 form a gate bias circuit of the FET Q.sub.1, and in this example a voltage bias is applied to the gate G of the FET from the gate bias power supply 9 which is provided outside the dielectric substrate 1, through the gate bias bonding pad P.sub.1. Here, the electric length of the transmission line T.sub.1 is usually established at one fourth wavelength of the microwave signal and the end terminal of the transmission line T.sub.1 is grounded at high frequencies via the capacitor C.sub.1. Therefore, viewed at the gate of the FET Q.sub.1, the impedance of the transmission line T.sub.1 becomes infinite, which prevents the microwave signal from leaking to the gate G of the FET through the gate-source or the gate-drain capacitance of the FET Q.sub.1.
A resistor R.sub.1 can be used instead of the transmission line T.sub.1. In such case the value of the resistor R.sub.1, typically 1 K.OMEGA. which is sufficiently higher than characteristic impedance of the transmission line M.sub.1, typically 50 .OMEGA., prevents the microwave signal from leaking to the gate G of the FET through the gate-source or gate-drain capacitance of the FET Q.sub.1. Here, the resistor R.sub.1 can be a semiconductor layer or a thin film resistor.
The capacitor C.sub.1 also prevents a high frequency signal from being applied to the gate of the FET Q.sub.1 from outside of the dielectric substrate 1 through the gate bonding pad P.sub.1. Here, in the device of FIG. 12, although the capacitor C.sub.1 is grounded at the rear surface electrode via the grounding bonding pad P.sub.2, it can be grounded inside the dielectric substrate 1 using a via-hole.
The transmission line T.sub.2 is part of a source voltage bias circuit of the FET Q.sub.1 and, in this example, the source voltage bias circuit of the FET Q.sub.1 is grounded at the rear surface electrode 4. The electrical length of the transmission line T.sub.2 is established at one fourth wavelength of the microwave signal. Thus, similarly as in the case of the gate bias circuit, the microwave signal is prevented from leaking to the transmission line T.sub.2 from the transmission line M.sub.1. Here, when a second resistor R.sub.2 is used in place of the transmission line T.sub.2, establishing the value of the resistor R.sub.2 at a value, typically 1 k.OMEGA., sufficiently higher than the characteristic impedance of the transmission line M.sub.1, typically 50 .OMEGA. prevents the leakage of the microwave signal.
In the semiconductor integrated circuit as described above, the attenuation of the microwave signal input from the RF input terminal 7 is controlled by varying the gate bias voltage of the FET Q.sub.1, more concretely by varying the drain-source resistance of the FET Q.sub.1 in a range from a sufficiently small value of several .OMEGA. to a sufficiently large value of several M.OMEGA., thereby enabling producing of a signal from the RF output terminal 8.
In the above-described prior art example, the electrical length of the transmission line T.sub.2 is established at one fourth wavelength, but a microwave switching circuit which can short-circuit or open circuit the microwave signal input from the RF output terminal 8 at the FET Q.sub.1 can be obtained by directly grounding the source S of the FET Q.sub.1 with the transmission line T.sub.2 and the transmission line M1 can be dispensed with.
FIG. 13 is a plan view showing a semiconductor integrated circuit constituting a high frequency switch which is a prior art example of a semiconductor integrated circuit using a semi-insulating semiconductor substrate. FIG. 14 is a cross sectional view thereof and schematically shows the FET, the via-hole, and the connecting relation between them and the transmission lines T.sub.1 and T.sub.2. In FIG. 13, the same reference numerals as those shown in FIGS. 10 and 11 designate the same elements. A semi-insulating semiconductor substrate 14 is used in place of the dielectric substrate in the semiconductor integrated circuit shown in FIGS. 10 to 12 and the source S and the drain D of the FET Q.sub.1 are connected to the rear surface electrode 4 via the substrate resistor 6. Here, because the bias circuit of the source S is provided externally, the second transmission line T.sub.2 and the via-hole V are not used for connecting the source S to the rear surface electrode.
FIG. 15 shows an equivalent circuit of the semiconductor integrated circuit of FIG. 13. In FIG. 15, reference numeral 6 designates a substrate resistance between the source S, drain D and the rear surface electrode 4. The same reference numerals as those shown in FIG. 12 designate the same portions.
The operation of the circuit of FIG. 13 will be described with reference to the equivalent circuit of FIG. 15.
In the equivalent circuit of FIG. 15, since there is no transmission line T.sub.2 and no via-hole V as shown in FIG. 12, source bias is applied from outside of the semi-insulating semiconductor substrate 1 using a circuit construction for applying DC bias such as a bias tee. In the case of using a semi-insulating semiconductor substrate 1, a substrate resistance 6 exists between the rear surface electrode 4 and the source S or the drain D of the FET as shown in FIG. 14, differently from the case of using a semi-insulating dielectric substrate such as sapphire substrate. The value of this substrate resistance 6 is usually more than 1 M.OMEGA.. Therefore, the circuit operation is similar to that of the equivalent circuit of FIG. 12.
The prior art semiconductor integrated circuit which has a construction as described above, where the gate of the FET Q.sub.1 is insulated from the source or the drain of the FET Q.sub.1 with respect to DC signals, has the following problem. That is, in a process of fabricating a semiconductor integrated circuit such as a chip separation process, pure water which flows over a wafer while cutting a semiconductor integrated circuit substrate with a dicing-saw causes electrostatic charging of the gate bias circuit, that is, electrification of the bonding pads for the gate, the source, and the drain which are not covered with passivation films, and this results electrostatic breakdown of the gate.
In Japanese Patent Publication No. Sho. 60-47469 is recited a Schottky gate field effect transistor in which a pn junction element having a series resistance lower than that of the gate electrode is connected in parallel with the gate electrode and the source or drain electrode, whereby the gate electrode is protected from an impulse voltage applied from the outside.
However, since the resistance of the pn junction element is smaller than the serial resistance of the gate, the impedance at the gate changes and impedance matching is not achieved in the microwave circuit. As a result, leakage or reflection of the input microwave signal arises.
In the Japanese Patent Publication No. Sho. 61-30078 is recited a microwave band high output transistor in which the gate electrode and the grounding electrode are connected to each other by a diffusion region produced directly below the gate pad and thus avoidance of the gate destruction is attempted. However, even in this construction the resistance value of the diffusion region is only about 200 .OMEGA., and there also arises a problem of impedance mismatching.